Cost-Effective Development of Proprietary Analog IP

The independent development of innovative proprietary analog IP has always been a challenge for small design firms such as MIE Labs.  Such firms are typically self-funded through the design service revenues that they generate.  The process of taking a circuit concept through the entire design cycle through prototype validation is very costly and time consuming.  Without a paying customer behind this effort, this scope of effort is rarely justifiable or even feasible.  On the other hand, having a growing library of innovative analog IP is critical for the efficient development of analog IC products as well as providing a level of comfort to prospective customers that technical risk has been addressed to the greatest extent possible prior to undertaking a challenging product design effort.  The development of this sort of IP library can also provide a potential second source of revenue to the firm in the form of royalties and/or license fees to better support the operations of the design team, further enabling future IP development.

One compromise approach which addresses this issue of proprietary analog IP development is to have internal staff undertake to quickly and effectively develop new IP concepts only to the point that their performance characteristics can be readily demonstrated.  This can be accomplished in a cost-effective manner through the use of behavioral modeling and simulation.  Utilizing this approach, innovative circuit and system concepts can be relatively quickly evaluated and demonstrated.  Potential problem areas and critical performance limitations can be identified early in the development process.  Behavioral simulation models which include some non-idealities reflective of the real (transistor-level) analog circuits are utilized and therefore provide a reasonable level of confidence that performance demonstrated in a behavioral simulation can in fact be realized in a full transistor-level design moving forward.  In some cases actual transistor-level components and existing IP modules can be included in a mixed behavioral/transistor simulation (for example, actual output power FET models and parasitics used in a power switching device) in order to better represent the expected behavior of the real circuitry.

Through the judicious use of this approach, many analog circuit and product ideas can be explored quickly to a reasonable level, giving a better sense of what may be accomplished in a full transistor-level design implementation.  This technique goes a long way in demonstrating concepts and capabilities to prospective customers and partners.   Rather than simply present a draft data sheet and/or a block diagram, actual simulation results can be demonstrated under various operating conditions and specific tradeoffs can be explored ahead of time with significantly less upfront design effort.  MIE Labs is using this approach right now to flesh out some interesting analog product and IP concepts which we believe will greatly benefit our customers and partners moving forward.  If you would like to find out more, please feel free to contact me at echalfin@mielabs.com.